Via and through-hole parasitics
Via inductance, parasitic capacitance and circumference. A plated through-hole via carries inductive and capacitive parasitics like any other structure. Read the via circumference as a rough answer to "how wide a trace is this via equivalent to?"
Advanced — Clearance hole diameter, PCB relative permittivity
History
Formula
(h: via height [mm], d: via diameter [mm])
Parasitic capacitance: C = 0.55×εr×T×d/(D−d) [pF]
Design notes
Vias are how you get between layers, but they bring inductance and capacitance with them. In the GHz range the impedance discontinuity at a via is a real source of signal degradation.
What to do about it on fast designs:
• Back-drill to remove the unused stub, which otherwise resonates
• Use a smaller via diameter to cut the inductance
• Put ground vias next to signal vias so the return current has somewhere to go
The circumference output tells you what trace width a via is worth, which is the number you want when sizing vias for current.
When you need this
For working out decoupling capacitor placement and the effect of high-speed nets changing layer. How much a single via costs you in inductance is probably the most commonly overlooked term in power distribution design.
Why via inductance matters
A decoupling capacitor is not defined by its own ESL alone. Everything from the pad through the via down to the power and ground planes is in series with it.
A via through a 1.6mm board is about 1.3nH. Against the roughly 0.5nH ESL of an 0402 capacitor, two vias — power and ground — contribute more than five times the capacitor itself. Paying for a low-ESL part achieves nothing if the vias are poorly arranged.
Effect on resonant frequency
A capacitor is only capacitive up to its self-resonant frequency; above that it is inductive. With total inductance L and capacitance C the resonance sits at f = 1/(2π√(LC)).
A 100nF capacitor on its own (0.5nH ESL) resonates at about 22MHz. Add 2.6nH for two vias, giving 3.1nH, and it falls to about 9MHz — about 40% of the band you were aiming at.
The most effective lever is making vias shorter: inductance scales almost linearly with height. Simply placing the power and ground planes near the surface in your stack-up buys you this for free.
Typical values
| Board thickness (via length) | Via diameter | Inductance | Capacitance |
|---|---|---|---|
| 1.6mm | φ0.3mm | about 1.30 nH | about 0.38 pF |
| 1.6mm | φ0.2mm | about 1.43 nH | about 0.38 pF |
| 0.8mm | φ0.3mm | about 0.54 nH | about 0.19 pF |
| 2.4mm | φ0.3mm | about 2.14 nH | about 0.57 pF |
How to reduce it
- Shorten the via. Put power and ground planes just under the surface. This is the biggest single win.
- Add vias — but two do not halve it. Adjacent vias couple magnetically, so you typically get 60–70%. To get real benefit they must be spaced apart.
- Remove the trace between pad and via. Use via-in-pad or place the via against the pad. Even 0.5mm of escape routing adds roughly 0.3nH.
- Put the power and ground vias close together. The currents are anti-parallel, so proximity cancels flux and lowers loop inductance.
Common mistakes
- Selecting on capacitor ESL alone. Mounted inductance is set by the vias and routing. The difference between a 0.3nH and 0.5nH part is noise next to 1.3nH of via.
- Reaching for "two vias" as a reflex. Coupling limits the benefit. Either space them out or, better, make them shorter.
- Ignoring the capacitance. On high-speed differential nets, via capacitance shows up as an impedance dip. Above 10Gbps you may need back-drilling to remove unused stubs.
Frequently asked questions
Do two vias halve the inductance?
When should I care about via capacitance?
Should I always use via-in-pad?
What is back-drilling?
Standards and references
- IPC-2221B — Via dimensions and land design.
- Howard Johnson, "High-Speed Digital Design" — Via inductance and decoupling implementation.
- Montrose, "EMC and the Printed Circuit Board" — Via parasitics and their EMI consequences.
Last updated: 2026-08-29
Columns on this calculation
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